Half Adder
Consider adding two binary numbers together:We see that the bit in the "two's" column is generated when the addition carried over. A halfadder is a circuit which adds two bits together and outputs the sum of those two bits. The halfadder has two outputs: sum and carry. Sum represents the remainder of the integer division A+B/2, while carry is the result. This can be expressed as follows:

Full Adder
Halfadders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multibit numbers. However, the two output bits of a halfadder can also represent the result A+B=3 as sum and carry both being high.As such, the fulladder can accept three bits as an input. Commonly, one bit is referred to as the carryin bit. Full adders can be cascaded to produce adders of any number of bits by daisychaining the carry of one output to the input of the next.

RippleCarry Adder
A ripple carry adder is simple several full adders connected in a series so that the carry must propagate through every full adder before the addition is complete. Ripple carry adders require the least amount of hardware of all adders, but they are the slowest.The following diagram shows a fourbit adder, which adds the numbers A[3:0] and B[3:0], as well as a carry input, together to produce S[3:0] and the carry output.
Propagation Delay in Full Adders
Real logic gates do not react instantaneously to the inputs, and therefore digital circuits have a maximum speed. Usually, the delay through a digital circuit is measured in gatedelays, as this allows the delay of a design to be calculated for different devices. AND and OR gates have a nominal delay of 1 gatedelay, and XOR gates have a delay of 2, because they are really made up of a combination of ANDs and ORs.A full adder block has the following worst case propagation delays:
 From A_{i} or B_{i} to C_{i+1}: 4 gatedelays (XOR → AND → OR)
 From A_{i} or B_{i} to S_{i}: 4 gatedelays (XOR → XOR)
 From C_{i} to C_{i+1}: 2 gatedelays (AND → OR)
 From C_{i} to S_{i}: 2 gatedelays (XOR)
 4 gatedelays from generating the first carry signal (A_{0}/B_{0} → C_{1}).
 2 gatedelays per intermediate stage (C_{i} → C_{i+1}).
 2 gatedelays at the last stage to produce both the sum and carryout outputs (C_{n1} → C_{n} and S_{n1}).
CarryLookahead Adder
A fast method of adding numbers is called carrylookahead. This method doesn't require the carry signal to propagate stage by stage, causing a bottleneck. Instead it uses additional logic to expedite the propagation and generation of carry information, allowing fast addition at the expense of more hardware requirements.In a ripple adder, each stage compares the carryin signal, C_{i}, with the inputs A_{i} and B_{i} and generates a carryout signal C_{i+1} accordingly. In a carrylookahed adder, we define two new function.
The generate function, G_{i}, indicates whether that stage causes a carryout signal C_{i} to be generated if no carryin signal exists. This occurs if both the addends contain a 1 in that bit:
A_{i}  B_{i}  C_{i}  G_{i}  P_{i}  C_{i+1}  

0  0  0  0  0  0  
0  0  1  0  0  0  
0  1  0  0  1  0  
0  1  1  0  1  1  
1  0  0  0  1  0  
1  0  1  0  1  1  
1  1  0  1  1  1  
1  1  1  1  1  1 
Operation  Required Data  Gate Delays 

Produce stage generate and propagate signals  Addends (a and b)  1 
Produce stage carryout signals, C_{1} to C_{n}  P and G signals, and C_{0}  2 
Produce sum result, S  Carry signals and addends  3 
Total  6 
For a slightly smaller circuit, the propagate signal can be taken as the output of the first XOR gate instead of using a dedicated OR gate, because if both A and B are asserted, the generate signal will force a carry. However, this simplifiaction means that the propagate signal will take two gate delays to produce, rather than just one.
A carry lookahead adder then contains n PFAs and the logic to produce carries from the stage propagate and generate signals:
Two numbers can therefore be added in constant time, O(1), of just 6 gate delays, regardless of the length, n of the numbers. However, this requires AND and OR gates with up to n inputs. If logic gates are available with a limited number of inputs, trees will need to be constructed to compute these, and the overall computation time is logarithmic, O(ln(n)), which is still much better than the linear time for ripple adders.
Cascading CarryLookahead Adders
A basic carrylookahead adder is very fast but has the disadvantage that it takes a very large amount of logic hardware to implement. In fact, the amount of hardware needed is approximately quadratic with n, and begins to get very complicated for n greater than 4.Due to this, most CLAs are constructed out of "blocks" comprising 4bit CLAs, which are in turn cascaded to produce a larger CLA.
CarrySave Adder
This section of the Digital Circuits wikibook is a stub. You can help by expanding this section. If you add something, list yourself as a Contributor.A carrysave adder is a kind of adder with low propagation delay (critical path), but instead of adding two input numbers to a single sum output, it adds three input numbers to an output pair of numbers. When its two outputs are then summed by a traditional carrylookahead or ripplecarry adder, we get the sum of all three inputs.
When adding three or more numbers together, a sequence of carrysave adders terminated by a single carrylookahead adder provides much better propagation delays than a sequence of carrylookahead adders. In particular, the propagation delay of a carrysave adder is not affected by the width of the vectors being added.
Carrysave adders are really completely parallel arrays of full adder circuits, with the each bit of the three input vectors loaded into each full adder's A, B, and Cin inputs. Each full adder's output S is connected to the corresponding output bit of one output, and its output Cout is connected to the next higher output bit of the second output; the lowest bit of the second output is fed directly from the carrysave's Cin input.
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